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Arvind Pawan R.
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www.cvitae.org/rarvind.bits/
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Resume
last modified 2009-04-06 20:52:46 | |

CVitae -
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To pursue graduate studies and further research in the field of solid state electronics and nanotechnology. |
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BITS, Pilani, M.Sc (Hons.) Physics / B.E (Hons.) EEE
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- CGPA: 9.50 / 10 Core GPA: 10 / 10
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Undergraduate Theses, Tata Institute of Fundamental Research, Mumbai, India
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Summer Internship, Tata Institute of Fundamental Research, Mumbai, India
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Summer Internship, Indira Gandhi Centre for Atomic Research, Kalpakkam, India
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- Worked with prof. E.L.Terrence in the Physical Metallurgical Division on analysis of data from an Electron Probe Micro Analyzer. (EPMA)
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Recepient of SIA-NOL scholarship by the Government of Singapore for undergraduate study in NUS |
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Was one among 60 students all over India to have been awarded Summer Research Fellowship by JNCASR, Bangalore, India |
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Was one among 6 students all over India selected for TIFR's Visiting Student's Research programme |
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Among top 1% at the national level in the International Physics Olympiad |
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SKILLS, TECHNOLOGIES & PROJECTS
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Software Packages: MATLAB, LABView |
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Hardware Description Languages: Verilog, VHDL |
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High Level Languages: C, C++ |
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Design Automation Tools: NC Verilog, Model Sim, Eldo Spice, Virtuoso, Cadence |
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Technology CAD Tools: Silvaco - Atlas and Athena, MEDICI |
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Assembly Languages: Intel 8086, TMS 320 C5x, C6x |
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will be provided upon request
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Connections
 Dirk Englund
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